This invention is related to an output circuit for an IC (integrated circuit) whose output is prevented from generating a spike noise at a starting time when the source voltage is building up in the IC.
In many of the output circuits of IC devices especially in output circuits of CMOS (complementary metal oxide semiconductor) devices a click noise or spike noise is generated at the start of operation, namely when the voltage source is switched on and the device begins to operate. Usually such initial spike noise is very small and harmless since the source of voltage has not sufficiently built up and it is low compared to the operating voltage of the ICs, hence the spike is very small. However, a problem can occur if the circuit or device which receives the output of the IC comprises a sensitive circuit such as flip-flop circuit or latch circuit which is already in an operating condition to be driven by small pulse.
The spike noise is generated in the inner logic circuit of the IC, at the start of operation. One reason for generation of such spike noise is considered to be due to the interaction between the build-up phenomena of the source voltage V.sub.cc and the threshold voltages V.sub.th for various transistors, especially in enhancement type transistors forming the logic circuit of the IC. Namely, when the voltage supply source is switched on and the gate voltage is increased over the threshold voltage V.sub.th, the transistor drain current begins to flow, but since the threshold voltage of each transistor is different, drain current flow is random. Thus, at the start of the IC operation, there is an instant when the logic circuit operates in a disorderly fashion, and an excess pulse is generated. The probability of generating such initial spike noise is increased as the IC increases in complexity.
In order to avoid malfunction in following stages of the system caused by the initial spike noise of the IC, a reset circuit has been provided between the IC and the following stage of the system, and the system was kept waiting until the foregoing stage IC began its normal operation. However, such a technique requires a long time until the entire system is ready for normal operation. Moreover, it requires rather complicated reset circuits at many points in the system.